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Xpeedic to Exhibit at WSCE2020

Date: July 20-24, 2020

Place: Nanjing, China

Booth: X12


Xpeedic Technology will showcase its latest solutions at the2020 World Semiconductor Conference 2020 (WSCE) on August 26-28.

On the basis of the 2019 world semiconductor conference, the conference will further focus on the new trends, new trends and new products of the industry, provide international cooperation and exchange platform, and promote the rapid development of the semiconductor industry.

Xpeedic 5G solution enables designers inSoC, RFIC, packaging, board to build better 5G systems with theirdifferentiating technologies. It includes the following highlights:

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IC Category

On-chip passive modeling and simulation for RF and high performance analog designs for mobile, connectivity and optical applications
  • RFIC Passive Simulation
  • Analog/Mix Signal IC Passive Simulation
  • RF PDK Turn Key Solution

Package Category

Package modeling and simulation ranging from low cost packages to high performance interposer with TSV for mobile, networking and server applications

  • RFFE Module Simulation
  • Advanced Package Simulation
  • System in Package Simulation

System Category

Package and board level Signal Integrity analysis for high speed digital system designs in servers, storage and networking

  • RF PCB System Simulation
  • High Speed Digital System Simulation
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More details to see here.
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Xpeedic to Exhibit at IMS2020

Date: Aug 4-6, 2020

A Virtual Experience ( Click here to enter Xpeedic Virtual Booth)

Xpeedic will showcase its latest 5G RF solution at the 2020 IEEE MTT-S International Microwave Symposium (IMS) .

Xpeedic RF solution spans from IC, filter, to package. Its on-chip passive modeling and simulation tool IRIS, certified by foundries, helps RFIC designers to achieve first-pass silicon success. Its package extraction tool Metis enables fast package extraction for RF SiP. Its filter design tool XDS provides a complete flow from schematic, layout, to post-layout simulation to design IPD, SAW, and BAW filters. Xpeedic RF solution further enables RF front end miniaturization with the IPD designs from spec to volume production.


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EDA-IC

IRIS enables on-chip passive modeling and simulation for RFIC designs. With its accelerated 3D EM solver, advanced process support, and seamless Virtuoso integration, IRIS helps RFIC designers to achieve first-pass silicon success.

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EDA-Package

Metis provides fast package modeling and simulation for various package types. It supports System-in-Package (SiP) which is getting more and more adoption with the 5G RF front end being more modularized. It also supports IC-package co-simulation so that package impact can be captured.

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EDA-Filter

The newly release XDS is a dedicated tool for RF filter designs. It provides a complete filter design flow from schematic to layout to post-layout co-simulation. It supports multiple filter types including IPD, SAW, and BAW. Built-in filter topology for quick schematic creation, built-in spec libraries, auto layout generation, tuning and optimization make filter designs easier.

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IP-IPD

Xpeedic advanced IPD technology to enable passive integration for 5G RF front end, helping customers to achieve faster design convergence from spec to volume production.


Xpeedic will also present at IMS MicroApps  and Industry Workshop:

MicroApps

TUMA8

Industry Workshop

IW13AB


Click here to enter Xpeedic Virtual Booth.

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Xpeedic to Exhibit at DAC2020

【As the premier conference for the design and design automation of electronic circuits and systems, the 57th DAC (Design Automation Conference) program has expanded to also include many verticals closely integrated with and/or dependent on cutting-edge electronic design automation. Along with a large exhibit floor featuring top EDA, design on cloud and IP companies, stellar keynote sessions and endless networking, the topics below will be represented on both the industry and academia portions of the DAC program.】

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Date: July 20-24, 2020

A Virtual Experience

Xpeedic Technology will showcase its latest solutions at the2020 Design Automation Conference (DAC) on July 20-24.

Xpeedic 5G solution enables designers inSoC, RFIC, packaging, board to build better 5G systems with theirdifferentiating technologies. It includes the following highlights:

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1. High Speed High Frequency EDA Solution

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  IC Category

On-chip passive modeling and simulation for RF and high performance analog designs for mobile, connectivity and optical applications
  • RFIC Passive Simulation
  • Analog/Mix Signal IC Passive Simulation
  • RF PDK Turn Key Solution

334

Package Category

Package modeling and simulation ranging from low cost packages to high performance interposer with TSV for mobile, networking and server applications

  • RFFE Module Simulation
  • Advanced Package Simulation
  • System in Package Simulation

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System Category

Package and board level Signal Integrity analysis for high speed digital system designs in servers, storage and networking

  • RF PCB System Simulation
  • High Speed Digital System Simulation

2. Foundry Technology Support

Xpeedic EDA supports mainstream foundry nodes, including:

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3. Xpeedic Cloud Platform on AWS

Xpeedic cloud solution built on Amazon Elastic Compute Cloud (EC2) supports a wide range of instant types including the compute-optimized ones and the memory-intensive ones. Xpeedic’s EM solver technologies support both multi-core parallelism and distributed computing, which makes them suitable for cloud computing. Xpeedic’s own job scheduler JobQueue manages the computer resource and prioritizes the simulation jobs. With the near infinite resource available in the AWS cloud, Xpeedic can now help its customers to achieve scalability for their most demanding simulation jobs.

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More details to see here.

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Xpeedic to Exhibit at DesignCon 2020

Date: Jan.28-30, 2020

Location: Santa Clara, CA

Booth#: 645

Xpeedic Technology, Inc. will exhibit at DesignCon 2020 at Santa Clara on Jan.28-30, 2020.

DesignCon is the premier conference for chip, board and systems design engineers in the high speed communications and semiconductor communities. The DesignCon Expo Hall offers the latest products and technologies in signal integrity and high-speed design for your current and future projects. You can test and compare emerging tools and technologies from top tier vendors.

At Booth 645, Xpeedic will showcase their latest update in RF front end miniaturization solution and high speed signal integrity (SI) solution in the conference. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications. Their fast and accurate SI software enables the quick way to simulate the high speed channel for both pre-layout and post-layout scenarios.

Live Demo Highlights include:

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What's more, Xpeedic, together with Cisco, will jointly publish a paper entitled . Details are as follows:

  • Time: Thursday, January 30 | 2:50pm – 3:30pm
  • Speakers: Anna Gao (Cisco Systems, Inc.), Feng Ling (Xpeedic Technology, Inc.)
  • Authors: Kevin Cai (Cisco Systems, Inc.), Bidyut Sen (Cisco Systems, Inc.), Joshua Wan (Xpeedic Technology, Inc.)
  • Location: Ballroom E
  • Track: 13. Modeling & Analysis of Interconnects, 12. Applying Test & Measurement Methodology

Click here to register now and use Xpeedic's exclusive VIP registration code “SPECIAL” to get 20% off the full price.

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Xpeedic to Exhibit at ICCAD 2019

Date: Nov.21-22, 2019 Location: Nanjing, China Booth#: 045-046 Xpeedic Technology, Inc. will exhibit at CSIA-ICCAD 2019 Annual Conference & Nanjing IC Industry Innovation and Development Summit (ICCAD 2019) in Nanjing on Nov.21-22, 2019. ICCAD is a most important annual event for IC design industry in China. It creates a biggest platform for enterprises within China IC industry chain […]

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SiP Conference China 2019

Date: Sept 10-11, 2019
Place: Shenzhen, China

SiP Conference China 2019 is the third System-in-Package (SiP) conference in China fully dedicated to covering all aspects related to SiPs business and technology to meet current and future SiP challenges. The conference features inspiring sparkers from entire SiP supply and design chain from OEM, Fabless, IDM, OSAT, EMS, EDA, silicon foundries, equipment and material suppliers together to one place in Shenzhen, China.

The arrival of 5G and Artificial intelligent (AI) technology is having a massive impact on wireless, IoT, autonomous and connected vehicles, automated smart cities, base stations, data storage, computing and networking. The conference and exhibition will highlight System in Package technologies that are helping to implement cost effective solutions of electronic components integration in small size SiP packaging. The program will include several keynote speakers and technical sessions, followed by a panel discussion of key issues, including SiP assembly and test, advancement in materials and substrates and system solutions for targeted market applications.

The conference will cover the following vital topics:

  • SiP Business and Technology Trends
  • SiP System Solutions for Smartphone and IoT
  • 5G NR & mmWave SiP Solutions
  • 2.5D/3D and WLSiP Applications, Assembly and Test Challenges
  • Advance Material & Substrate Solutions for SiP
  • provide dynamic learning and technology updates for SiP related trends

Dr.Feng Ling, CEO of Xpeedic Technology will lead the session during the conference. Dr. Wenliang Dai, co-founder, VP Engineering, will present “Enabling SiP Design with Differentiating Simulation Technologies” within SiP Design Challenges forum on Sept.11. Xpeedic team will also demonstrate its latest SiP, IPD and related EDA solutions and products then.

 For more details, please click here.
 General chair

sip-nk  General Chair:Nozad Karim  VP, Product Line SiP, Amkor Technology

Nozad Karim presently is the Vice President of SiP & System Integration at Amkor Technology. He has over 20 years’ experience with SiP & module technology developments, and over 30 years of experience working with semiconductor packaging, circuit and system designs for digital, analog, and RF/Microwave applications. Prior to Amkor, he served in engineering and management roles with Motorola Communication, Texas Instruments, & Compaq Computer.

Technical chair

sip-dv  Techinical Chair:David Lu  VP, New Technology Research Institute vivo Mobile Communication Co., Ltd.

With over 25+ years experience in electronics process engineering, material science and technology strategic planning, David is leading innovative assembly technology development for high volume manufacturing operation of consumer electronics, including smartphones, smartwatches, SiP modules, automotive modules, tablets, PC, etc. David has spent many years on Design for Manufacturing (DFM), developed DFX design guidelines, wrote assembly process specifications & standards, established NPI (New Product Introduction) verification facilities and audited EMS outsourcing. Prior to Huawei, David also held a several senior and principal technical positions in Nokia Mobile Phones, Nortel Networks and Alcatel. David is also holding several technology patents in US, Europe and China, leading industrial consortium and external technology collaboration and actively providing keynote presentations and speeches in conferences, seminar and training courses with international background and East-meets-West culture & multi-language capabilities.

Technical chair

sip-rb  Technical Chair:Rozalia Beica  VP of Technology, IMAPS

Rozalia Beica is currently Global Director Strategic Marketing with DowDuPont. She is focusing on strategic activities, identifying new technologies and markets, growth opportunities across Electronics & Imaging Division. She has 25 years of international working experience across various industries, including industrial, electronics and semiconductors. For 18 years she was involved in the research, applications and strategic marketing of Advanced Packaging, with global leading responsibilities at specialty chemicals (Rohm and Haas), equipment (Semitool, Applied Materials and Lam Research) and device manufacturing (Maxim IC). Prior to joining Dow, Rozalia was the CTO of Yole Developpement where she led the market research, technology and strategy consulting activities for Advanced Packaging and Semiconductor Manufacturing.

session leader

sip-fl  Session Leader: Feng Ling  CEO, Xpeedic Technology

Feng Ling (S’97-M’00-SM’07) is currently Founder and CEO of Xpeedic Technology, Inc., a leading EDA software and IP provider in chip-package-system solution. In 2000, he was a Senior Staff Engineer/Scientist at Motorola (now Freescale Semiconductor), working on RF module technology with LTCC and HDI substrate. In 2002, he joined Neolinear, where he led the electromagnetic solver development for mixed-signal RF integrated circuit designs. Through Cadence acquisition of Neolinear, he joined Cadence in 2004. As VP of Engineering, he co-founded Physware in 2007 (acquired by Mentor Graphics in 2014). In 2010, he founded Xpeedic Technology, Inc., continuing the efforts to bring the novel solution to the RF design and high speed digital community. Dr. Ling received his Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign (UIUC) in 2000. He is a Senior Member of IEEE. He has authored and co-authored 2 book chapters and more than 60 papers in refereed journals and conference proceedings. He has served on the technical program committee of DesignCon, EDAPS, and EPTC. He has 5 US patents. He was the inaugural recipient of the Y. T. Lo Outstanding Research Award from the Department of Electrical and Computer Engineering at UIUC in 1999. He has been an Affiliate Associate Professor in the Department of Electrical Engineering at the University of Washington, Seattle, WA from 2007 to 2011.

session leader

sip-rm  Session Leader:Rahul Maneplli  Director of Engineering for Substrate Package Technology Development, Intel

Rahul Manepalli is a Sr. Principal Engineer and the Director of Module Engineering in Substrate and Package Technology Development Group in Intel Corporation. Rahul manages the Module Engineering group responsible for development of next generation Substrate and Package Technologies for all of Intel’s packaging needs. He has over 20 years of experience in Packaging (Assembly & Substrate materials, processes and modules) and has lead the startup and development of multiple Intel factories and Technology Development teams. He holds over 40 + worldwide patents in the area of electronic packaging and has a Ph.D. in Chemical Engineering from the Georgia Institute of Technology.

session leader

sip-jk  Session Leader: Jingkun Mao  Vice General Manager, SRCT Tec

1998 and 2000, respectively. He received his Ph.D. degree in Electrical Engineering from the University of Missouri-Rolla in 2004. From 2004 to 2009, he worked for Amkor Technology Inc., Phoenix, AZ, as a RF Packaging Engineer. Then, he joined the Third Research Institute of MPS, as a Director of Engineer. In July 2012, he joined the SRCT Tech. Co. Ltd, currently serves as the vice general manager. His research interests include signal integrity and EMI designs in high-speed digital systems, dc power-bus modeling, intra-system EMI and RF interference, PCB noise reduction,differential signaling, and package designs.

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Xpeedic to Exhibit at IMS2019

Date: June 2-7, 2019

Place: Boston, US

Booth#: 210


Xpeedic Technology will showcase its latest solutions at the 2019 IEEE MTT-S International Microwave Symposium (IMS) in Boston Convention & Exhibition Center, June 2-7.

Featured as in-booth demos will include

  • IRIS, Virtuoso-integrated EM simulation tool with the state-of-the-art 3D planar solver

Certified on multiple foundries’ advanced process nodes and proven on RF IC designs including 5G mmWave.

  • Metis, IC-package co-simulation tool

IC-package co-simulation tool to enable system-in-package designs. It also supports advanced packaging technologies such as 2.5D interposer with TSV.

  • IPD for RF FE module design

Advanced IPD technology to enable passive integration for RF front end, helping customers to achieve faster design convergence from spec to volume production.

  • Through Glass Via (TGV) solution in collaboration with Corning

Through Glass Via technology has become a promising technology candidate to realize integrated, low cost and high performance passive devices. A diplexer built with TGV shows less in-band insertion loss and greater out-of-band rejection yet still compact size.


Xpeedic will also present at IMS MicroApps Theatre

* Title: Integrated Passive Devices (IPD) for RF Front End Integration (WEMA35)

* Time: June 5, 12:30-12:45



See the event details here.

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Xpeedic to Exhibit at DAC2019

Date: June 2-6, 2019

Place: Las Vegas, NV, US

Booth#:622

Xpeedic Technology will showcase its latest solutions at the 2019 Design Automation Conference (DAC) in Las Vegas, June 2-6.

Xpeedic 5G solution enables designers inSoC, RFIC, packaging, board to build better 5G systems with theirdifferentiating technologies. It includes the following highlights:

dac-5g

5G RFIC in Advanced Process Nodes
  • IRIS,Virtuoso-integrated EM simulation tool with the state-of-the-art 3D planar solver, certified on multiple foundries’ advanced process nodes and proven on RF IC designs including 5G mmWave.

IC-Package Co-design for 5G Application
  • Metis,IC-package co-simulation tool to enable 5G system-in-package designs, and supports advanced packaging technologies for CPU, GPU, network processor, FPGA designs to enable artificial intelligence applications in 5G era.

Integrated Passive Devices for 5G NR
  • RF front end module has become more and more complicated with mobile technology evolving from 2G, 3G, 4G to 5G. Increasing number of bands, carrier aggregation, and MIMO demand more filters and more integration in RF front end. Integrated passive devices (IPD) provide great advantages of miniaturization, high consistency, low cost and high integration over discrete. Xpeedic has partnered with industry leading IPD foundries with both silicon and glass substrates. With the extensive IPD design experience,Xpeedic helps customers to choose the right technology to meet their spec.

More details to see here.